Design of Power Gated True Single-Phase-Clocked Flip-Flop

Pratiman Singh

Dept of ECE, College of SVNIT, Surat, Gujarat

Dr Prashant K Shah

Dept of ECE, College of SVNIT, Surat, Gujarat

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http://doi.org/10.37648/ijrst.v12i03.002

Abstract

References

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